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rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? 2003 analog devices, inc. all rights reserved. ad9753 * 12-bit, 300 msps high speed txdac+ ? d/a converter * protected by u.s. patent numbers 5450084, 5568145, 5689257, and 5703519. other patents pending. features 12-bit dual muxed port dac 300 msps output update rate excellent sfdr and imd performance sfdr to nyquist @ 25 mhz output: 69 db internal clock doubling pll differential or single-ended clock input on-chip 1.2 v reference single 3.3 v supply operation power dissipation: 155 mw @ 3.3 v 48-lead lqfp applications communications: lmds, lmcs, mmds base stations digital synthesis qam and ofdm functional block diagram avdd acom refio fsadj port1 i outa i outb ad9753 dvdd dcom latch latch clk+ clk clkvdd pllvdd clkcom reset lpf div0 div1 plllock pll clock multiplier dac latch dac reference mux port2 general description the ad9753 is a dual, muxed port, ultrahigh speed, single- channel, 12-bit cmos dac. it integrates a high quality 12-bit txdac+ core, a voltage reference, and digital interface circuitry into a small 48-lead lqfp package. the ad9753 offers excep- tional ac and dc performance while supporting update rates up to 300 msps. the ad9753 has been optimized for ultrahigh speed applica- tions up to 300 msps where data rates exceed those possible on a single data interface port dac. the digital interface consists of two buffered latches as well as control logic. these latches can be time multiplexed to the high speed dac in several ways. this pll drives the dac latch at twice the speed of the exter- nally applied clock and is able to interleave the data from the two input channels. the resulting output data rate is twice that of the two input channels. with the pll disabled, an external 2 clock may be supplied and divided by two internally. the clk inputs (clk+/clk? can be driven either differen- tially or single-ended, with a signal swing as low as 1 v p-p. the dac utilizes a segmented current source architecture combined with a proprietary switching technique to reduce glitch energy and to maximize dynamic accuracy. differential current outputs support single-ended or differential applica- tions. the differential outputs each provide a nominal full-scale current from 2 ma to 20 ma. the ad9753 is manufactured on an advanced low cost 0.35 m cmos process. it operates from a single supply of 3.0 v to 3.6 v and consumes 155 mw of power. product highlights 1. the ad9753 is a member of a pin compatible family of high speed txdac+s providing 10-, 12-, and 14-bit resolution. 2. ultrahigh speed 300 msps conversion rate. 3. dual 12-bit latched, multiplexed input ports. the ad9753 features a flexible digital interface allowing high speed data conversion through either a single or dual port input. 4. low power. complete cmos dac function operates on 155 mw from a 3.0 v to 3.6 v single supply. the dac full- scale current can be reduced for lower power operation. 5. on-chip voltage reference. the ad9753 includes a 1.20 v temperature-compensated band gap voltage reference.
rev.b e2e ad9753especifications parameter min typ max unit resolution 12 bits dc accuracy 1 integral linearity error (inl) e1.5 0.5 +1.5 lsb differential nonlinearity (dnl) e1 0.4 +1 lsb analog output offset error e0.025 0.01 +0.025 % of fsr gain error (without internal reference) e2 0.5 +2 % of fsr gain error (with internal reference) e2 0.25 +2 % of fsr full-scale output current 2 2.0 20.0 ma output compliance range e1.0 +1.25 v output resistance 100 k output capacitance 5 pf reference output reference voltage 1.14 1.20 1.26 v reference output current 3 100 na reference input input compliance range 0.1 1.25 v reference input resistance 1 m temperature coefficients offset drift 0 ppm of fsr/ c gain drift (without internal reference) 50 ppm of fsr/ c gain drift (with internal reference) 100 ppm of fsr/ c reference voltage drift 50 ppm/ c power supply supply voltages avdd 3.0 3.3 3.6 v dvdd 3.0 3.3 3.6 v pllvdd 3.0 3.3 3.6 v clkvdd 3.0 3.3 3.6 v analog supply current (i avdd ) 4 33 36 ma digital supply current (i dvdd ) 4 3.5 4.5 ma pll supply current (i pllvdd ) 4 4.5 5.1 ma clock supply current (i clkvdd ) 4 10.0 11.5 ma power dissipation 4 (3 v, i outfs = 20 ma) 155 165 mw power dissipation 5 (3 v, i outfs = 20 ma) 216 mw power supply rejection ratio 6 ?avdd e1 +1 % of fsr/v power supply rejection ratio 6 ?dvdd e0.04 +0.04 % of fsr/v operating range e40 +85 c notes 1 measured at i outa , driving a virtual ground. 2 nominal full-scale current, i outfs , is 32 the i ref current. 3 an external buffer amplifier is recommended to drive any external load. 4 100 msps f dac with pll on, f out = 1 mhz, all supplies = 3.0 v. 5 300 msps f dac . 6 5% power supply variation. specifications subject to change without notice. dc specifications (t min to t max , avdd = 3.3 v, dvdd = 3.3 v, pllvdd = 3.3 v, clkvdd = 3.3 v, i outfs = 20 ma, unless otherwise noted.)
rev. b ad9753 e3e parameter min typ max unit dynamic performance maximum output update rate (f dac ) 300 msps output settling time (t st ) (to 0.1%) 1 11 ns output propagation delay (t pd ) 1 1ns glitch impulse 1 5 pv-s output rise time (10% to 90%) 1 2.5 ns output fall time (10% to 90%) 1 2.5 ns output noise (i outfs = 20 ma) 50 pa/ hz hz hz hz hz hz hz hz hz hz hz hz hz hz hz hz hz hz hzhz hzhz hzhz h hz hz hz hz hz hz hzhz
rev. b e4e ad9753 digital specifications (t min to t max , avdd = dvdd = pllvdd = clkvdd = 3.3 v, i outfs = 20 ma, unless otherwise noted.) parameter min typ max unit digital inputs logic 1 2.1 3 v logic 0 0 0.9 v logic 1 current e10 +10 a logic 0 current e10 +10 a input capacitance 5 pf input setup time (t s ), t a = 25 c 1.0 0.5 ns input hold time (t h ), t a = 25 c 1.0 0.5 ns latch pulsewidth (t lpw ), t a = 25 c 1.5 ns input setup time (t s , pllvdd = 0 v), t a = 25 c e1.0 e1.5 ns input hold time (t h , pllvdd = 0 v), t a = 25 c 2.5 1.7 ns clk to plllock delay (t d , pllvdd = 0 v), t a = 25 c 3.5 4.0 ns latch pulsewidth (t lpw pllvdd = 0 v), t a = 25 c 1.5 ns pllock (v oh ) 3.0 v pllock (v ol ) 0.3 v clk inputs input voltage range 0 3 v common-mode voltage 0.75 1.5 2.25 v differential voltage 0.5 1.5 v min clk frequency * 6.25 mhz * min clk frequency applies only when using internal pll. when pll is disabled, there is no minimum clk frequency. specifications subject to change without notice.
rev. b ad9753 e5e caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad9753 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. port 1 data x data y t h t s t lpw t pd data x data y t pd port 2 i outa or i outb input clk (pll enabled) data in figure 1. i/o timing ordering guide temperature package package model range description option AD9753AST e40 c to +85 c 48-lead lqfp st-48 AD9753ASTrl e40 c to +85 c 48-lead lqfp st-48 ad9753-eb evaluation board thermal characteristic thermal resistance 48-lead lqfp ja = 91 c/w absolute maximum ratings * parameter with respect to min max unit avdd, dvdd, clkvdd, pllvdd acom, dcom, clkcom, pllcom e0.3 +3.9 v avdd, dvdd, clkvdd, pllvdd avdd, dvdd, clkvdd, pllvdd e3.9 +3.9 v acom, dcom, clkcom, pllcom acom, dcom, clkcom, pllcom e0.3 +0.3 v refio, reflo, fsadj acom e0.3 avdd + 0.3 v i outa , i outb acom e1.0 avdd + 0.3 v digital data inputs (db13 to db0) dcom e0.3 dvdd + 0.3 v clk+/clke, plllock clkcom e0.3 clkvdd + 0.3 v div0, div1, reset clkcom e0.3 clkvdd + 0.3 v lpf pllcom e0.3 pllvdd + 0.3 v junction temperature 150 c storage temperature e65 +150 c lead temperature (10 sec) 300 c * stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating on ly; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposu re to absolute maximum ratings for extended periods may affect device reliability.
rev. b e6e ad9753 pin function descriptions pin no. mnemonic description 1 reset internal clock divider reset 2 clk+ differential clock input 3 clke differential clock input 4, 22 dcom digital common 5, 21 dvdd digital supply voltage 6 plllock phase-locked loop lock indicator output 7e18 p1b11ep1b0 data bits db11 to db0, port 1 19e20, 35e36 reserved 23e34 p2b11ep2b0 data bits db11 to db0, port 2 37, 38 div0, div1 control inputs for pll and input port selector mode. see tables i and ii for details. 39 refio reference input/output 40 fsadj full-scale current output adjust 41 avdd analog supply voltage 42 i outb differential dac current output 43 i outa differential dac current output 44 acom analog common 45 clkcom clock and phase-locked loop common 46 lpf phase-locked loop filter 47 pllvdd phase-locked loop supply voltage 48 clkvdd clock supply voltage pin configuration 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 37 43 42 41 40 pin 1 identifier top view (not to scale) 36 35 34 33 32 31 30 29 28 27 26 25 ad9753 reserved reserved p2b0elsb p2b1 p2b2 p2b3 p2b4 p2b5 p2b6 p2b7 p2b8 p2b9 reset clk+ clke dcom dvdd plllock msbep1b11 p1b10 p1b9 p1b8 p1b7 p1b6 clkvdd pllvdd lpf clkcom acom i outa i outb avdd fsadj refio div1 div0 p1b5 p1b4 p1b3 p1b2 p1b1 lsbep1b0 reserved reserved dvdd dcom msbep2b11 p2b10 reserved = no user connections
rev. b ad9753 e7e terminology linearity error (also called integral nonlinearity or inl) linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. differential nonlinearity (dnl) dnl is the measure of the variation in analog value, normalized to full scale, associated with a 1 lsb change in digital input code. monotonicity a d/a converter is monotonic if the output either increases or remains constant as the digital input increases. offset error the deviation of the output current from the ideal of zero is called offset error. for i outa , 0 ma output is expected when the inputs are all 0s. for i outb , 0 ma output is expected w hen all inputs are set to 1s. gain error the difference between the actual and ideal output span. the actual span is determined by the output when all inputs are set to 1s, minus the output when all inputs are set to 0s. output compliance range the range of allowable voltage at the output of a current-output dac. operation beyond the maximum compliance limits may cause either output stage saturation or breakdown, resulting in nonlinear performance. temperature drift specified as the maximum change from the ambient (25 c) value to the value at either t min or t max . for offset and gain drift, the drift is reported in ppm of full-scale range (fsr) per degree celsius. for reference drift, the drift is reported in ppm per degree celsius. power supply rejection the maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages. settling time the time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition. glitch impulse asymmetrical switching times in a dac give rise to undesired output transients that are quantified by a glitch impulse. it is specified as the net area of the glitch in pv-s. spurious-free dynamic range the difference, in db, between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth. total harmonic distortion (thd) thd is the ratio of the rms sum of the first six harmonic com- ponents to the rms value of the measured fundamental. it is expressed as a percentage or in decibels (db). signal-to-noise ratio (snr) snr is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the n yquist frequency, excluding the first six harmonics and dc. the value for snr is expressed in decibels. adjacent channel power ratio (acpr) a ratio in dbc between the measured power within a channel relative to its adjacent channel. ad9753 i outa i outb segmented switches for db0 to db11 dac fsadj refio 1.2v ref clk+ plllock digital data inputs 0.1 f r set 2k 1k 50 mini circuits t1-1t to rohde & schwarz fsea30 spectrum analyzer db0 e db11 tektronix dg2020 or awg2021 w/option 4 lecroy 9210 pulse generator (for data retiming) dcom pmos current source array avdd 3.0v to 3.6v dvdd 2e1 mux port 1 latch dac latch acom port 2 latch clke pll circuitry pllvdd clkvdd reset lpf clkcom div0 div1 50 db0 e db11 mini circuits t1-1t 1k 3.0v to 3.6v hp8644 signal generator pll enabled pll disabled figure 2. basic ac characterization test setup
rev. b e8e ad9753etypical performance characteristics f out (mhz) 90 70 40 35 5 0 sfdr (dbc) 80 60 50 10 15 20 25 30 0dbmfs e6dbmfs e12dbmfs tpc 1. single-tone sfdr vs. f out @ f dac = 65 msps, single-port mode f out (mhz) 90 70 40 100 0 sfdr (dbc) 80 60 50 20 40 60 80 120 140 200msps 300msps 65msps tpc 4. sfdr vs. f out @ 0 dbfs a out (db) 90 70 40 e6 e16 sfdr (dbc) 80 60 50 e14 e12 e10 e8 e4 e2 0 11.82mhz @ 130msps 18.18mhz @ 200msps 27.27mhz @ 300msps tpc 7. single-tone sfdr vs. a out @ f out = f dac /11 f out (mhz) 90 70 40 100 10 0 sfdr (dbc) 80 60 50 20 30 40 50 60 70 80 90 0dbmfs e6dbmfs e12dbmfs tpc 2. single-tone sfdr vs. f out @ f dac = 200 msps f out (mhz) 90 70 40 100 10 0 sfdr (dbc) 80 60 50 20 30 40 50 60 70 80 90 sfdr near carriers (2f1-f2, 2f2-f1) sfdr over nyquist band tpc 5. two-tone imd vs. f out @ f dac = 200 msps, 1 mhz spacing between tones, 0 dbfs a out (dbm) 90 70 40 e6 e16 sfdr (dbc) 80 60 50 e14 e12 e10 e8 e4 e2 0 26mhz @ 130msps 40mhz @ 200msps 60mhz @ 300msps tpc 8. single-tone sfdr vs. a out @ f out = f dac /5 f out (mhz) 90 70 40 100 0 sfdr (dbc) 80 60 50 20 40 60 80 120 140 160 0dbmfs e6dbmfs e12dbmfs tpc 3. single-tone sfdr vs. f out @ f dac = 300 msps f out (mhz) 90 70 40 100 0 sfdr (dbc) 80 60 50 20 40 60 80 120 140 160 sfdr close to carriers (2f1-f2, 2f2-f1) sfdr over nyquist band tpc 6. two-tone imd vs. f out @ f dac = 300 msps, 1 mhz spacing between tones, 0 dbfs a out (dbm) 90 70 40 e6 e16 sfdr (dbc) 80 60 50 e14 e12 e10 e8 e4 e2 0 e18 e20 18.18mhz/19.18mhz @ 200msps 11.82mhz/12.82mhz @ 130msps 27.27mhz/28.27mhz @ 300msps tpc 9. two-tone imd (third order products) vs. a out @ f out = f dac /11
rev. b ad9753 e9e a out (dbm) 90 70 40 e6 e16 sfdr (dbc) 80 60 50 e14 e12 e10 e8 e4 e2 0 e18 e20 18.18mhz/19.18mhz @ 200msps 11.82mhz/12.82mhz @ 130msps 27.27mhz/28.27mhz @ 300msps tpc 10. two-tone imd (to nyquist) vs. a out @ f out = f dac /11 f dac (mhz) 90 70 85 300 50 sinad (dbm) 80 60 50 100 150 200 250 75 65 55 tpc 13. sinad vs. f dac @ f out = 10 mhz, 0 dbfs code 0 e0.4 4095 511 0 inl (lsb) 0.2 e0.2 1023 1535 2047 3071 e0.6 3583 0.6 2559 0.1 0.4 tpc 16. typical inl a out (dbm) 90 70 40 e6 e16 sfdr (dbc) 80 60 50 e14 e12 e10 e8 e4 e2 0 e18 e20 60mhz/61mhz @ 300msps 26mhz/27mhz @ 130msps 40mhz/41mhz @ 200msps tpc 11. two-tone imd (third order products) vs. a out @ f out = f dac /5 f out (mhz) 75 65 50 160 20 0 sfdr (dbc) 70 60 55 40 60 80 100 120 45 40 140 i outfs = 20ma i outfs = 10ma i outfs = 5ma tpc 14. sfdr vs. i outfs , f dac = 300 msps @ 0 dbfs code 4095 511 0 dnl (lsb) 0.50 1023 1535 2047 3071 e0.02 3583 0.54 2559 0.46 0.42 0.38 0.34 0.30 0.26 0.22 0.18 0.14 0.10 0.06 0.02 tpc 17. typical dnl a out (dbm) 90 70 40 e6 e16 sfdr (dbc) 80 60 50 e14 e12 e10 e8 e4 e2 0 e18 e20 60mhz/61mhz @ 300msps 26mhz/27mhz @ 130msps 40mhz/41mhz @ 200msps tpc 12. two-tone imd (to nyquist) vs. a out @ f out = f dac /5 temperature ( c ) 75 65 50 90 e30 e50 sfdr (dbc) 70 60 55 e10 10 30 50 45 40 70 80 10mhz 40mhz 120mhz 80mhz tpc 15. sfdr vs. temperature, f dac = 300 msps @ 0 dbfs frequency (mhz) e10 e30 e80 20 0 amplitude (dbm) e20 e40 e75 40 60 100 120 e95 e100 140 0 e50 e60 80 f dac = 300msps f out1 = 24mhz f out2 = 25mhz f out3 = 26mhz f out4 = 27mhz f out5 = 28mhz f out6 = 29mhz f out7 = 30mhz f out8 = 31mhz sfdr = 58dbc magnitude = 0dbfs 0 tpc 18. eight-tone sfdr @ f out f dac /11, f dac = 300 msps
rev. b e10e ad9753 ad9753 i outa i outb segmented switches for db0 to db11 dac fsadj refio 1.2v ref div0 plllock digital data inputs 0.1 f r set 2k r load 50 db0 e db11 dcom pmos current source array avdd 3.0v to 3.6v dvdd 2e1 mux port 1 latch dac latch acom port 2 latch div1 pll circuitry pllvdd clkvdd clk+ clke clkcom reset lpf db0 e db11 v out b r load 50 v out a v diff = v out a e v out b figure 3. simplified block diagram functional description figure 3 shows a simplified block diagram of the ad9753. the ad9753 consists of a pmos current source array capable of providing up to 20 ma of full-scale current, i outfs . the array is divided into 31 equal sources that make up the five most significant bits (msbs). the next four bits, or middle bits, consist of 15 equal current sources whose value is 1/16th of an msb current source. the remaining lsbs are a binary weighted fraction of the middle bit current sources. implementing the middle and lower bits with current sources, instead of an r-2r ladder, enhances dynamic performance for multitone or low amplitude signals and helps maintain the dac?s high output impedance (i.e., >100 k ). all of the current sources are switched to one of the two outputs (i.e., i outa or i outb ) via pmos differential current switches. the switches are based on a new architecture that drastically improves distortion performance. this new sw itch architecture reduces various timing errors and provides matching complementary drive signals to the inputs of the differential current switches. the analog and digital sections of the ad9753 have separate power supply inputs (i.e., avdd and dvdd) that can operate independently over a 3.0 v to 3.6 v range. the digital section, which is capable of operating at a 300 msps clock rate, consists of edge-triggered latches and segment decoding logic circuitry. the analog section includes the pmos current sources, the associated differential switches, a 1.20 v band gap voltage refer- ence, and a reference control amplifier. the full-scale output current is regulated by the reference con trol amplifier and can be set from 2 ma to 20 ma via an external resistor, r set . the external resistor, in combination with both the reference control amplifier and voltage reference v refio , sets the reference current i ref , which is replicated to the seg mented current sources with the proper scaling factor. the full-scale current, i outfs , is 32 times the value of i ref . reference operation the ad9753 contains an internal 1.20 v band gap reference. this can easily be overdriven by an external reference with no effect on performance. refio serves as either an input or output, depending on whether the internal or an external reference is used. to use the internal reference, simply decouple the refio pin to acom with a 0.1 f capacitor. the internal reference voltage will be present at refio. if the voltage at refio is to be used elsewhere in the circuit, an external buffer amplifier with an input bias current less than 100 na should be used. an example of the use of the internal reference is given in figure 4. a low impedance external reference can be applied to refio, as shown in figure 5. the external reference may provide either a fixed reference voltage to enhance accuracy and drift perfor- mance or a varying reference voltage for gain control. note that the 0.1 f compensation capacitor is not required since the internal reference is overdriven, and the relatively high input impedance of refio minimizes any loading of the external reference. 1.2v ref avdd i ref current source array refio fsadj 2k 0.1 f ad9753 reference section additional external load optional external reference buffer figure 4. internal reference configuration 1.2v ref avdd i ref current source array refio fsadj 2k ad9753 reference section external reference avdd figure 5. external reference configuration
rev. b ad9753 e11e port 1 data x data y t h t s t lpw t pd data x data y 1/2 cycle + t pd port 2 i outa or i outb clk data in figure 7a. dac input timing requirements with pll active, single clock cycle port 1 data x data z data x data y port 2 i outa or i outb clk data in data z data w xxx data w data y figure 7b. dac input timing requirements with pll active, multiple clock cycles typically, the vco can generate outputs of 100 mhz to 400 mhz. the range control is used to keep the vco operating within its designed range, while allowing input clocks as low as 6.25 mhz. with the pll active, logic levels at div0 and div1 determine the divide (prescaler) ratio of the range controller. table i gives the frequency range of the input clock for the different states of div0 and div1. table i. clk rates for div0, div1 levels with pll active clk frequency div1 div0 range controller 50 mhze150 mhz 0 0 1 25 mhze100 mhz 0 1 2 12.5 mhze50 mhz 1 0 4 6.25 mhze25 mhz 1 1 8 a 392 resistor and 1.0 f capacitor connected in series from lpf to pllvdd are required to optimize the phase noise versus the settling/acquisition time characteristics of the pll. to obtain optimum noise and distortion performance, pllvdd should be set to a voltage level similar to dvdd and clkvdd. in general, the best phase noise performance for any pll range control setting is achieved with the vco operating near its m axi- mum output frequency of 400 mhz. as stated earlier, applications requiring input data rates below 6.25 msps must disable the pll clock multiplier and provide an external 2 reference clock. at higher data rates however, applications already containing a low phase noise (i.e., jitter) reference control amplifier the ad9753 also contains an internal control amplifier that is used to regulate the dac?s full-scale output current, i outfs . the control amplifier is configured as a voltage-to-current converter as shown in figure 4, so that its current output, i ref , is determined by the ratio of v refio and an external resistor, r set , as stated in equation 4. i ref is applied to the segmented current sources with the proper scaling factor to set i outfs , as stated in equation 3. the control amplifier allows a wide (10:1) adjustment span of i outfs over a 2 ma to 20 ma range by setting i ref between 62.5 a and 625 a. the wide adjustment span of i outfs provides several application benefits. the first benefit relates directly to the power dissipation of the ad9753, which is proportional to i outfs (refer to the power dissipation section). the second benefit relates to the 20 db adjustment, which is useful for system gain control purposes. the small signal bandwidth of the reference control amplifier is approximately 500 khz and can be used for low frequency, small signal multiplying applications. pll clock multiplier operation the phase-locked loop (pll) is intrinsic to the operation of the ad9753 in that it produces the necessary internally syn- chronized 2 clock for the edge-triggered latches, multiplexer, and dac. with pllvdd connected to its supply voltage, the ad9753 is in pll mode. figure 6 shows a functional block diagram of the ad9753 clock control circuitry with pll active. the circuitry consists of a phase detector, charge pump, voltage controlled oscillator (vco), input data rate range control, clock logic circuitry, and control input/outputs. the 2 logic in the feed- back loop allows the pll to generate the 2 clock needed for the dac output latch. clkcom to input latches clkvdd (3.0v to 3.6v) plllock charge pump phase detector lpf pllvdd vco 392 1.0 f 3.0v to 3.6v range control ( 1, 2, 4, 8) div0 div1 differential- to- single-ended amp 2 to dac latch clk+ clke ad9753 figure 6. clock circuitry with pll active figure 7 defines the input and output timing for the ad9753 with the pll active. clk in figure 7 represents the clock that is generated external to the ad9753. the input data at both ports 1 and 2 is latched on the same clk rising edge. clk may be applied as a single-ended signal by tying clke to midsupply and applying clk to clk+, or as a differential signal applied to clk+ and clke. reset has no purpose when using the internal pll and should be grounded. when the ad9753 is in pll mode, plllock is the output of the internal phase detector. when locked, the lock output in this mode will be a logic 1.
rev. b e12e ad9753 reference clock that is twice the input data rate should consider disabling the pll clock multiplier to achieve the best snr performance from the ad9753. note, the sfdr performance of the ad9753 remains unaffected with or without the pll clock multiplier enabled. the effects of phase noise on the ad9753?s snr performance become more noticeable at higher reconstructed output fre quen- cies and signal levels. figure 8 compares the phase noise of a full-scale sine wave at exactly f data /4 at different data rates (thus carrier frequency) with the optimum div1, div0 set ting. snr is partly a function of the jitter generated by the clock circuitry. as a result, any noise on pllvdd or clkvdd may decrease the snr at the output of the dac. to minimize this potential problem, pllvdd and clkvdd can be connected to dvdd using an lc filter network similar to the one shown in figure 9. frequency offset ( mhz ) 0 e20 e110 5 1 0 noise density (dbm/hz) e10 e30 e40 e50 e60 e70 e80 e90 e100 234 pll on, f data = 150msps pll off, f data = 50msps figure 8. phase noise of pll clock multiplier at f out = f data /4 at different f data settings with div0/div1 optimized, using r&s fsea30 spectrum analyzer 100 f elect. 10 f tant. 0.1 f cer. ttl/cmos logic circuits 3.3v power supply ferrite beads clkvdd pllvdd clkcom figure 9. lc network for power filtering dac timing with pll active as described in figure 7, in pll active mode, port 1 and port 2 input latches are updated on the rising edge of clk. on the same rising edge, data previously present in the input port 2 latch is written to the dac output latch. the dac output will update after a short propagation delay (t pd ). following the rising edge of clk at a time equal to half of its period, the data in the port 1 latch will be written to the dac output latch, again with a corresponding change in the dac output. due to the internal pll, the time at which the data in the port 1 and port 2 input latches is written to the dac latch is independent of the duty cycle of clk. when using the pll, the external clock can be operated at any duty cycle that meets the specified input pulsewidth. on the next rising edge of clk, the cycle begins again with the t wo input port latches being updated, and the dac output latch being updated with the current data in the port 2 input latch. pll disabled mode when pllvdd is grounded, the pll is disabled. an external clock must now drive the clk inputs at the desired dac out- put update rate. the speed and timing of the data present at input ports 1 and 2 are now dependent on whether or not the ad9753 is interleaving the digital input data or only responding to data on a single port. figure 10 is a functional block diagram of the ad9753 clock control circuitry with the pll disabled. pllvdd to dac latch plllock clock logic ( 1 or 2) differential- to- single-ended amp to internal mux clkin+ clkine ad9753 reset div0 div1 to input latches figure 10. clock circuitry with pll disabled div0 and div1 no longer control the pll but are used to set the control on the input mux for either interleaving or non- interleaving the input data. the different modes for states of div0 and div1 are given in table ii. table ii. input mode for div0, div1 levels with pll disabled input mode div1 div0 interleaved (2 )0 0 noninterleaved port 1 selected 0 1 port 2 selected 1 0 not allowed 1 1
rev. b ad9753 e13e interleaved (2 ) mode with pll disabled the relationship between the internal and external clocks in this mode is shown in figure 11. a clock at the output update data rate (2 the input data rate) must be applied to the clk inputs. internal dividers then create the internal 1 clock necessary for the input latches. although the input latches are updated on the rising edge of the delayed internal 1 clock, the setup-and-hold times given in the digital specifications table are with respect to the rising edge of the external 2 clock. with the pll disabled, a load-dependent delayed version of the 1 clock is present at the plllock pin. this signal can be used to synchronize the external data. port 1 data x data y t h t s t lpw t pd data x data y port 2 i outa or i outb delayed internal 1 clk data in t pd t d data enters input latches on this edge external 2 clk external 1 clk @ plllock figure 11. timing requirements, interleaved (2 ) mode with pll disabled updates to the data at input ports 1 and 2 should be synchro- nized to the specific rising edge of the external 2 clock that corresponds to the rising edge of the 1 internal clock, as shown in figure 11. to ensure synchronization, a logic 1 must be momentarily applied to the reset pin. doing this and return- ing reset to logic 0 brings the 1 clock at plllock to a logic 1. on the next rising edge of the 2 clock, the 1 clock will go to logic 0. on the second rising edge of the 2 clock, the 1 clock (plllock) will again go to logic 1, as well as update the data in both of the input latches. the details of this are shown in figure 12. reset plllock external 2 clock t rh = 1.2ns t rs = 0.2ns data enters input latches on these edges figure 12. reset function timing with pll disabled for proper synchronization, sufficient delay must be present between the time reset goes low and the rising edge of the 2 clock. reset going low must occur either at least t rs ns before the rising edge of the 2 clock, or t rh ns afterwards. in the first case, the immediately occurring clk rising edge will cause plllock to go low. in the second case, the next clk rising edge will toggle plllock. noninterleaved mode with pll disabled if the data at only one port is required, the ad9753 interface can operate as a simple double buffered latch with no interleaving. on the rising edge of the 1 clock, input latch 1 or 2 is updated with the present input data (depending on the state of div0/ div1). on the next rising edge, the dac latch is updated and a time t pd later, the dac output reflects this change. figure 13 represents the ad9753 timing in this mode. t h t s t lpw t pd data out port 1 or port 2 1 clock i outa or i outb xx data in port 1 or port 2 figure 13. timing requirements, noninterleaved mode with pll disabled dac transfer function the ad9753 provides complementary current outputs, i outa and i outb . i outa will provide a near full-scale current output, i outfs , when all bits are high (i.e., dac code = 4095), while i outb , the complementary output, provides no current. the current output appearing at i outa and i outb is a function of both the input code and i outfs and can be expressed as i outa = ( dac code /4096) i outfs (1) i outb = (4095 ? dac code )/4096 i outfs (2) where dac code = 0 to 4095 (i.e., decimal representation). as mentioned previously, i outfs is a function of the reference current, i ref , which is nominally set by a reference voltage, v refio , and an external resistor r set . it can be expressed as i outfs = 32 i ref (3) where i ref = v refio / r set (4) the two current outputs typically drive a resistive load directly or via a transformer. if dc coupling is required, i outa and i outb should be directly connected to matching resistive loads, r load , that are tied to analog common, acom. note that r load may represent the equivalent load resistance seen by i outa or i outb as would be the case in a doubly terminated 50 or 75 cable. the single-ended voltage output appearing at the i outa and i outb nodes is simply v outa = i outa r load (5) v outb = i outb r load (6) note that the full-scale values of v outa and v outb should not exceed the specified output compliance range to maintain specified distortion and linearity performance. v diff = ( i outa ?i outb ) r load (7)
rev. b e14e ad9753 substituting the values of i outa , i outb, and i ref , v diff can be expressed as v diff = {(2 dac code ?4095)/4096} (32 r load / r set ) v refio (8) these last two equations highlight some of the advantages of operating the ad9753 differentially. first, the differential op era- tion will help cancel common-mode error sources associated with i outa and i outb such as noise, distortion, and dc off sets. second, the differential code-dependent current and subsequent voltage, v diff , is twice the value of the single-ended voltage output (i.e., v outa or v outb ), thus providing twice the signal power to the load. note that the gain drift temperature performance for a single- ended (v outa and v outb ) or differential output (v diff ) of the ad9753 can be enhanced by selecting temperature tracking resistors for r load and r set due to their ratiometric relation- ship, as shown in equation 8. analog outputs the ad9753 produces two complementary current outputs, i outa and i outb , that may be configured for single-ended or differential operation. i outa and i outb can be converted into complementary single-ended voltage outputs, v outa and v outb , via a load resistor, r load , as described by equations 5 through 8 in the dac transfer function section. the differential volt age, v diff , existing between v outa and v outb , can also be con- verted to a single-ended voltage via a transformer or differential amplifier configuration. the ac performance of the ad9753 is optimum and specified using a differential transformer-coupled output in which the voltage swing at i outa and i outb is limited to 0.5 v. if a single-ended unipolar output is desirable, i outa should be selected as the output, with i outb grounded. the distortion and noise performance of the ad9753 can be enhanced when it is configured for differential operation. the common-mode error sources of both i outa and i outb can be significantly reduced by the common-mode rejection of a trans- former or differential amplifier. these common-mode error sources include even-order distortion products and noise. the enhancement in distortion performance becomes more signifi cant as the frequency content of the reconstructed waveform in creases. this is due to the first order cancellation of various dynamic common-mode distortion mechanisms, digital feedthrough, and noise. performing a differential-to-single-ended conversion via a trans- former also provides the ability to deliver twice the reconstructed signal power to the load (i.e., assuming no source termination). since the output currents of i outa and i outb are complemen- tary, they become additive when processed differentially. a properly selected transformer will allow the ad9753 to provide the required power and voltage levels to different loads. refer to the applying the ad9753 output configurations section for examples of various output configurations. the output impedance of i outa and i outb is determined by the equivalent parallel combination of the pmos switches associ- ated with the current sources and is typically 100 k in parallel with 5 pf. it is also slightly dependent on the output voltage (i.e., v outa and v outb ) due to the nature of a pmos device. as a result, maintaining i outa and/or i outb at a virtual ground via an i? op amp configuration will result in the optimum dc linearity. note that the inl/dnl specifications for the ad9753 are measured with i outa and i outb maintained at virtual ground via an op amp. i outa and i outb also have a negative and positive voltage com- pliance range that must be adhered to in order to achieve optimum performance. the negative output compliance range of ?.0 v is set by the breakdown limits of the cmos process. operation beyond this maximum limit may result in a breakdown of the output stage and affect the reliability of the ad9753. the positive output compliance range is slightly dependent on the full-scale output current, i outfs . it degrades slightly from its nominal 1.25 v for an i outfs = 20 ma to 1.00 v for an i outfs = 2 ma. the optimum distortion performance for a single- ended or differential output is achieved when the maximum full-scale signal at i outa and i outb does not exceed 0.5 v. applications requiring the ad9753? output (i.e., v outa and/ or v outb ) to extend its output compliance range should size r load accordingly. operation beyond this compliance range will ad versely affect the ad9753? linearity performance and subsequently degrade its distortion performance. digital inputs the ad9753? digital inputs consist of two channels of 14 data input pins each and a pair of differential clock input pins. the 12-bit parallel data inputs follow standard straight binary coding where db13 is the most significant bit (msb) and db0 is the l east significant bit (lsb). i outa produces a full-scale output current when all data bits are at logic 1. i outb produces a complementary output with the full-scale current split between the two outputs as a function of the input code. the digital interface is implemented using an edge-triggered master slave latch. with the pll active or disabled, the dac output is updated twice for every input latch rising edge, as shown in figures 7 and 11. the ad9753 is designed to support an input data rate as high as 150 msps, giving a dac output update rate of 300 msps. the setup-and-hold times can also be varied within the clock cycle as long as the specified mini- mum times are met. best performance is typically achieved when the input data transitions on the falling edge of a 50% duty cycle clock. the digital inputs are cmos compatible with logic thresholds, v threshold , set to approximately half the digital positive supply ( dvdd ) or v threshold = dvdd/ 2 ( 20%) the internal digital circuitry of the ad9753 is capable of oper- ating over a digital supply range of 3.0 v to 3.6 v. as a result, the digital inputs can also accommodate ttl levels when dvdd is set to accommodate the maximum high level voltage of the ttl drivers v oh (max). a dvdd of 3.0 v to 3.6 v typically ensures proper compatibility with most ttl logic families. figure 14 shows the equivalent digital input circuit for the data and clock inputs.
rev. b ad9753 e15e dvdd digital input figure 14. equivalent digital input the ad9753 features a flexible differential clock input operat- ing from separate supplies (i.e., clkvdd, clkcom) to achieve optimum jitter performance. the two clock inputs, clk+ and clke, can be driven from a single-ended or differ- ential clock source. for single-ended operation, clk+ should be driven by a logic source while clke should be set to the threshold voltage of the logic source. this can be done via a resistor divider/capacitor network, as shown in figure 15a. for differential operation, both clk+ and clke should be biased to clkvdd/2 via a resistor divider network, as shown in figure 15b. r series 0.1 f v threshold clk+ clkvdd clke clkcom ad9753 figure 15a. single-ended clock interface 0.1 f clk+ clkvdd clke clkcom ad9753 0.1 f 0.1 f figure 15b. differential clock interface because the output of the ad9753 can be updated at up to 300 msps, the quality of the clock and data input signals is important in achieving the optimum performance. the drivers of the digital data interface circuitry should be specified to meet the minimum setup-and-hold times of the ad9753 as well as its required min/max input logic level thresholds. digital signal paths should be kept short and run lengths matched to avoid propagation delay mismatch. inserting a low value resis- tor network (i.e., 20 to 100 ) between the ad9753 digital inputs and driver outputs may be helpful in reducing any over- shooting and ringing at the digital inputs that contribute to data feedthrough. for longer run lengths and high data update rates, strip line techniques with proper termination resistors should be considered to maintain clean digital inputs. the external clock driver circuitry should provide the ad9753 with a low jitter clock input meeting the min/max logic levels while providing fast edges. fast clock edges help minimize any jitter that will manifest itself as phase noise on a recon structed waveform. thus, the clock input should be driven by the fastest logic family suitable for the application. note that the clock input could also be driven via a sine wave that is centered around the digital threshold (i.e., dvdd/2) and meets the min/max logic threshold. this typically results in a slight degradation in the phase noise, which becomes more noticeable at higher sampling rates and output frequencies. a lso, at higher sampling rates, the 20% tolerance of the digital logic threshold should be considered since it will affect the effective clock duty cycle and, subsequently, cut into the required data setup-and-hold times. input clock and data timing relationship snr in a dac is dependent on the relationship between the position of the clock edges and the point in time at which the input data changes. the ad9753 is rising edge triggered, and so exhibits snr sensitivity when the data transition is close to this edge. in general, the goal when applying the ad9753 is to make the data transition close to the falling clock edge. this becomes more important as the sample rate increases. figure 16 shows the relationship of snr to clock placement with different sample rates. note that the setup-and-hold times implied in figure 16 appear to violate the maximums stated in the digital specifications of this data sheet. the variation in figure 16 is due to the skew present between data bits inherent in the digital data generator used to perform these tests. figure 16 is pre sented to show the effects of violating setup-and-hold times and to show the insensitivity of the ad9753 to clock placement when data transitions fall outside of the so-called bad window. the setup-and-hold times stated in the digital specifications table were measured on a bit-by-bit basis, therefore eliminating the skew present in the digital data generator. at higher data rates, it becomes very important to account for the skew in the input digital data when defining timing specifications. time of data transition relative to placement of clk rising edge (ns), f out = 10mhz, f dac = 300mhz 80 40 0 3 0 e3 snr (dbc) 60 20 70 30 50 10 e2 e1 1 2 figure 16. snr vs. time of data transition relative to clock rising edge power dissipation the power dissipation, p d , of the ad9753 is dependent on several factors that include the power supply voltages (avdd and dvdd), the full-scale current output i outfs , the update rate f clock , and the reconstructed digital input waveform. the power dissipation is directly proportional to the analog sup- ply current, i avdd , and the digital supply current, i dvdd . i avdd is directly proportional to i outfs , as shown in figure 17,
rev. b e16e ad9753 and is insensitive to f clock . conversely, i dvdd is dependent on both the digital input waveform, f clock , and digital supply, dvdd. figure 18 shows i dvdd as a function of the ratio (f out / f dac ) for various update rates. in addition, figure 19 shows the effect that the speed of f dac has on the pllvdd current, given the pll divider ratio. i outfs (ma) 40 20 0 20.0 10.0 0 i avdd (ma) 35 10 30 25 15 5 2.5 5.0 7.5 12.5 15.0 17.5 figure 17. i avdd vs. i outfs ratio (f ou t / f dac 20 16 0 1 0.01 0.001 i dvdd (ma) 18 14 12 10 8 6 4 2 0.1 300msps 200msps 100msps 50msps 25msps ) figure 18. i dvdd vs. f out /f dac ratio f dac (mhz) 10 0 300 150 0 pll_v dd (ma) 9 8 7 6 5 4 3 2 50 100 200 250 1 175 25 75 125 225 275 div setting 00 div setting 11 div setting 10 div setting 01 figure 19. pllvdd vs. f dac applying the ad9753 output configurations the following sections illustrate some typical output configura- tions for the ad9753. unless otherwise noted, it is assumed that i outfs is set to a nominal 20 ma. for applications requir- ing the optimum dynamic performance, a differential output configuration is suggested. a differential output configura tion may consist of either an rf transformer or a differential op amp configuration. the transformer configuration provides the opti- mum high frequency performance and is recommended for any application allowing for ac coupling. the differential op amp configuration is suitable for applications requiring dc coupling, a bipolar output, signal gain, and/or level shifting, within the bandwidth of the chosen op amp. a single-ended output is suitable for applications requiring a unipolar voltage output. a positive unipolar output voltage will result if i outa and/or i outb is connected to an appropri ately sized load resistor, r load , referred to acom. this con figu- ration may be more suitable for a single-supply system requiring a dc-coupled, ground referred output voltage. alterna tively, an amplifier could be configured as an i-v converter, thus con- verting i outa or i outb into a negative unipolar voltage. this configuration provides the best dc linearity since i outa or i outb is maintained at a virtual ground. note that i outa provides slightly better performance than i outb . differential coupling using a transformer an rf transformer can be used to perform a differential-to- single-ended signal conversion, as shown in figure 20. a differentially-coupled transformer output provides the optimum distortion performance for output signals whose spectral content lies within the transformer?s pass band. an rf transformer such as the mini-circuits t1-1t provides excellent rejection of common-mode distortion (i.e., even-order harmonics) and noise over a wide frequency range. when i outa and i outb are termi- nated to ground with 50 , this configuration provides 0 dbm power to a 50 load on the secondary with a dac full-scale current of 20 ma. a 2:1 transformer, such as the coilcraft wb2040-pc, can also be used in a configuration in which i outa and i outb are terminated to ground with 75 . this configura- tion improves load matching and increases power to 2 dbm into a 50 load on the secondary. transformers with different im ped- ance ratios may also be used for impedance matching purposes. note that the transformer provides ac coupling only. r load ad9753 mini-circuits t1-1t i outa i outb figure 20. differential output using a transformer the center tap on the primary side of the transformer must be connected to acom to provide the necessary dc current path for both i outa and i outb . the complementary voltages appearing at i outa and i outb (i.e., v outa and v outb ) swing symmetrically around acom and should be maintained with the specified output compliance range of the ad9753. a differ- ential resistor, r diff , may be inserted in applications where the output of the transformer is connected to the load, r load , via a
rev. b ad9753 e17e passive reconstruction filter or cable. r diff is determined by the transformer?s impedance ratio and provides the proper source termination that results in a low vswr. differential coupling using an op amp an op amp can also be used to perform a differential-to- single-ended conversion, as shown in figure 21. the ad9753 is configured with two equal load resistors, r load , of 25 . the differential voltage developed across i outa and i outb is con- verted to a single-ended signal via the differential op amp configuration. an optional capacitor can be installed across i outa and i outb , forming a real pole in a low-pass filter. the addition of this capacitor also enhances the op amp?s distor- tion performance by preventing the dac?s high slewing output from overloading the op amp?s input. ad9753 i outa i outb c opt 500 225 225 500 25 25 ad8047 figure 21. dc differential coupling using an op amp the common-mode rejection of this configuration is typically determined by the resistor matching. in this circuit, the dif- ferential op amp circuit using the ad8047 is configured to provide some additional signal gain. the op amp must operate from a dual supply since its output is approximately 1.0 v. a high speed amplifier capable of preserving the differential performance of the ad9753, while meeting other system level objectives (i.e., cost, power), should be selected. the op amp?s differential gain, its gain setting resistor values, and full-scale output swing capabilities should all be considered when opti- mizing this circuit. the differential circuit shown in figure 22 provides the neces- sary level-shifting required in a single-supply system. in this case, avdd, which is the positive analog supply for both the ad9753 and the op amp, is also used to level-shift the differen- tial output of the ad9753 to midsupply (i.e., avdd/2). the ad8041 is a suitable op amp for this application. ad9753 i outa i outb c opt 500 225 225 500 25 25 ad8041 1k avdd figure 22. single-supply dc differential coupled circuit single-ended unbuffered voltage output figure 23 shows the ad9753 configured to provide a unipolar output range of approximately 0 v to 0.5 v for a doubly termi- nated 50 cable since the nominal full-scale current, i outfs , of 20 ma flows through the equivalent r load of 25 . in this case, r load represents the equivalent load resistance seen by i outa or i outb . the unused output (i outa or i outb ) can be connected to acom directly or via a matching r load . different values of i outfs and r load can be selected as long as the positive compli- ance range is adhered to. one additional consideration in this mode is the integral nonlinearity (inl), as discussed in the analog outputs section. for optimum inl perform ance, the single- ended, buffered voltage output configuration is suggested. ad9753 i outa i outb 50 25 50 v outa = 0v to 0.5v i outfs = 20ma figure 23. 0 v to 0.5 v unbuffered voltage output single-ended buffered voltage output figure 24 shows a buffered single-ended output configuration in which the op amp performs an iev conversion on the ad9753 output current. the op amp maintains i outa (or i outb ) at a virtual ground, thus minimizing the nonlinear output imped- ance effect on the dac?s inl performance as discussed in the analog outputs section. although this single-ended configura- tion typically provides the best dc linearity performance, its ac distortion performance at higher dac update rates may be limited by the op amp?s slewing capabilities. the op amp pro- vides a negative unipolar output voltage and its full-scale output voltage is simply the product of r fb and i outfs . the full-scale output should be set within the op amp?s voltage output swing capabilities by scaling i outfs and/or r fb . an improve ment in ac distortion performance may result with a reduced i outfs , since the signal current the op amp will be required to sink will subsequently be reduced. ad9753 i outa i outb c opt 200 v out = i outfs r fb r fb 200 figure 24. unipolar buffered voltage output power and grounding considerations, power supply rejection many applications seek high speed and high performance under less than ideal operating conditions. in these applications, the implementation and construction of the printed circuit board is as important as the circuit design. proper rf techniques must be used for device selection, placement, and routing, as well as power supply bypassing and grounding, to ensure optimum performance. figures 34 to 41 illustrate the recommended printed circuit board ground, power, and signal plane layouts that are implemented on the ad9753 evaluation board. one factor that can measurably affect system performance is the ability of the dac output to reject dc variations or ac noise superimposed on the analog or digital dc power distribution.
rev. b e18e ad9753 this is referred to as the power supply rejection ratio. for dc variations of the power supply, the resulting performance of the dac directly corresponds to a gain error associated with the dac?s full-scale current, i outfs . ac noise on the dc supplies is common in applications where the power distribution is gener- ated by a switching power supply. typically, switching power supply noise will occur over the spectrum from tens of khz to several mhz. the psrr versus the frequency of the ad9753 avdd supply over this frequency range is shown in figure 25. frequency ( mhz ) 85 40 12 6 0 psrr (db) 80 75 70 65 60 55 50 45 24 810 figure 25. power supply rejection ratio note that the units in figure 25 are given in units of (amps out/ volts in). noise on the analog power supply has the effect of modulating the internal switches, and therefore the output current. the voltage noise on avdd will thus be added in a nonlinear manner to the desired i out . due to the relative different size of these switches, psrr is very code-depen dent. this can produce a mixing effect that can modulate low fre- quency power supply noise to higher frequencies. worst-case psrr for either one of the differential dac outputs will occur when the full-scale current is directed toward that output. as a result, the psrr measurement in figure 25 represents a worst- case condition in which the digital inputs remain static and the full-scale output current of 20 ma is directed to the dac out- put being measured. an example serves to illustrate the effect of supply noise on the analog supply. suppose a switching regulator with a switching frequency of 250 khz produces 10 mv rms of noise and, for simplicity sake (i.e., ignore harmonics), all of this noise is con- centrated at 250 khz. to calculate how much of this undesired noise will appear as current noise superimposed on the dac?s full-scale current, i outfs , one must determine the psrr in db using figure 25 at 250 khz. to calculate the psrr for a given r load , such that the units of psrr are converted from a/v to v/v, adjust the curve in figure 25 by the scaling factor 20 log (r load ). for instance, if r load is 50 , the psrr is reduced by 34 db, i.e., psrr of the dac at 250 khz, which is 85 db in figure 25, becomes 51 db v out /v in . proper grounding and decoupling should be a primary objective in any high speed, high resolution system. the ad9753 features separate analog and digital supply and ground pins to optimize the management of analog and digital ground currents in a system. in general, avdd, the analog supply, should be decoupled to acom, the analog common, as close to the chip as physically possible. similarly, dvdd, the digital supply, should be decoupled to dcom as close to the chip as physically possible. for those applications that require a single 3.3 v supply for both the analog and digital supplies, a clean analog supply may be generated using the circuit shown in figure 26. the circuit consists of a differential lc filter with separate power supply and return lines. lower noise can be attained by using low esr type electrolytic and tantalum capacitors. avdd acom 100 f elect. 10 f tant. 0.1 f cer. ttl/cmos logic circuits 3.3v power supply ferrite beads figure 26. differential lc filter for a single 3.3 v application applications qam/psk synthesis quadrature modulation (qam or psk) consists of two base- band pam (pulse amplitude modulated) data channels. both channels are modulated by a common frequency carrier. how- ever, the carriers for each channel are phase-shifted 90 from each other. this orthogonality allows twice the spectral effi ciency (data for a given bandwidth) of digital data transmitted via am. receivers can be designed to selectively choose the in phase and quadrature carriers, and then recombine the data. the recombi- nation of the qam data can be mapped as points representing digital words in a two dimensional constellation as shown in figure 27. each point, or symbol, represents the transmission of multiple bits in one symbol period. 0100 0101 0001 0000 0110 0111 0011 0010 1110 1111 1011 1010 1100 1101 1001 1000 figure 27. 16 qam constellation, gray coded (two 4-level pam signals with orthogonal carriers) typically, the i and q data channels are quadrature-modulated in the digital domain. the high data rate of the ad9753 allows extremely wideband (>10 mhz) quadrature carriers to be syn- thesized. figure 28 shows an example of a 25 msymbol/s qam signal, oversampled by 8 at a data rate of 200 msps, modu- lated onto a 25 mhz carrier and reconstructed using the ad9753. the power in the reconstructed signal is measured to be e11.92 dbm. in the first adjacent band, the power is e76.86 dbm, while in the second adjacent band, the power is e80.96 dbm.
rev. b ad9753 e19e e30 start 100khz e40 e50 e60 e70 e80 e90 e100 e110 e120 e130 12.49mhz/ stop 125mhz ref lv1 (dbm) 1rm e74.34dbm +9.71442886mhz e76.86dbm e80.96dbm e11.92dbm 1 [t1] ch pwr acp up acp low c11 c0 cu1 c11 c0 cu1 marker 1 [t1] rbw 5khz rf att 0db e74.34dbm vbw 50khz 9.71442886mhz swt 12.5 s unit dbm comment a: 25 msymbol, 64 qam, carrier = 25mhz 1 figure 28. reconstructed 64-qam signal at a 25 mhz if a figure of merit for wideband signal synthesis is the ratio of signal power in the transmitted band to the power in an adja- cent channel. in figure 28, the adjacent channel power ratio (acpr) at the output of the ad9753 is measured to be 65 db. the limitation on making a measurement of this type is often not the dac but the noise inherent in creating the digital data record using computer tools. to find how much this is limiting the perceived dac performance, the signal amplitude can be reduced, as is shown in figure 29. the noise contributed by the dac will remain constant as the signal amplitude is reduced. when the signal amplitude is reduced to the level where the noise floor drops below that of the spectrum analyzer, the acpr will fall off at the same rate that the signal level is being re duced. under the conditions measured in figure 28, this point occurs in figure 29 at e10 dbfs. this shows that the data record is actually degrading the measured acpr by up to 10 db. a single-channel active mixer such as the analog devices ad 8343 can then be used for the hop to the transmit frequency. figure 30 shows an applications circuit using the ad9753 and the ad 8343. the ad8343 is capable of mixing carriers from dc to 2.5 ghz. figure 31 shows the result of mixing the signal in figure 28 up to a carrier frequency of 800 mhz. acpr measured at the output of the ad8343 is shown in figure 31 to be 59 db. amplitude (dbfs) 80 60 40 0 e10 e20 acpr (db) 70 50 e15 e5 figure 29. acpr vs. amplitude for qam carrier dac latches dac input latches input latches pll/divider clk+ clke plllock dvdd av d d i outa i outb port 1 data input port 2 data input rset2 1.9k fsadj 0.1 f refio acom1 acom dcom ad9753 50 50 0.1 f 0.1 f 68 68 inpm inpp loim loip outp outm ad8343 active mixer 0.1 f 0.1 f loinput m/a-com etc-1-1-13 wideband balun figure 30. qam transmitter architecture using ad9753 and ad8343 active mixer
rev. b e20e ad9753 e20 center 860mhz e30 e40 e50 e60 e70 e80 e90 e100 e110 e120 11mhz/ span 110mhz ref lv1 (dbm) 2ma marker 1 [t2] rbw 10khz rf att 0db e99.88dbm vbw 10khz 859.91983968mhz swt 2.8 s unit dbm comment a: 25 msymbol , 64 qam carrier @ 825mhz e99.88bbm, +859.91983968mhz e65.67dbm e65.15dbm e7.05dbm 33.10db e49.91983968mhz 33.10db e49.91983968mhz 1 [t2] ch pwr acp up acp low 1 [t2] 2 [t2] c11 c11 c0 c0 cu1 cu1 1 1 2 figure 31. signal of figure 28 mixed to carrier frequency of 800 mhz effects of noise and distortion on bit error rate (ber) textbook analyses of bit error rate (ber) performance are generally stated in terms of e (energy in watts-per-symbol or watts-per-bit) and no (spectral noise density in watts/hz). for qam signals, this performance is shown graphically in figure 32. m represents the number of levels in each quadra- ture pam signal (i.e., m = 8 for 64 qam, m = 16 for 256 qam). figure 32 implies gray coding in the qam constellation, as well as the use of matched filters at the receiver, which is typical. the horizontal axis of figure 32 can be converted to units of energy/symbol by adding to the horizontal axis 10 log of the number of bits in the desired curve. for instance, to achieve a ber of 1e-6 with 64 qam, an energy per bit of 20 db is neces- sary. to calculate energy per symbol, we add 10 log(6), or 7.8 db. 64 qam with a ber of 1e-6 (assuming no source or chan nel coding) can therefore theoretically be achieved with an energy/symbol-to-noise (e/no) ratio of 27.8 db. due to the loss and interferers inherent in the wireless path, this signal-to- noise ratio must be realized at the receiver to achieve the given bit error rate. distortion effects on ber are much more difficult to deter mine accurately. most often in simulation, the energies of the stron gest distortion components are root-sum-squared with the noise, and the result is treated as if it were all noise. that being said, if the example above of 64 qam with the ber of 1e-6, using the e/ no ratio is much greater than the worst-case sfdr, the noise will dominate the ber calculation. the ad9753 has a worst-case in-band sfdr of 47 db at the upper end of its frequency spectrum (see tpcs 4 and 7). when used to synthesize high level qam signals as described above, noise, as opposed to distortion, will dominate its performance in these applications. snr/bit (db) 1ee0 1ee3 1ee6 20 5 0 symbol error probability 1ee2 1ee5 1ee1 1ee4 10 15 16 qam 64 qam 4 qam 20 figure 32. probability of a symbol error for qam pseudo zero stuffing/if mode the excellent dynamic range of the ad9753 allows its use in applications where synthesis of multiple carriers is desired. in addition, the ad9753 can be used in a pseudo zero stuffing mode that improves dynamic range at if frequencies. in this mode, data from the two input channels is interleaved to the dac, which is running at twice the speed of either of the input ports. however, the data at port 2 is held constant at midscale. the effect of this is shown in figure 33. the if signal is the image, with respect to the input data rate, of the fundamen- tal. normally, the sinx/x response of the dac will attenuate this im age. zero stuffing improves the pass-band flatness so that the image amplitude is closer to that of the fundamental sig- nal. z ero stuffing can be an especially useful technique in the synthesis of if signals. frequency (normalized to input data rate) 0 e30 2 0.5 0 effect of sinx/x roll-off e20 e50 e10 e40 1 1.5 amplitude of image without zero stuffing amplitude of image using zero stuffing figure 33. effects of pseudo zero stuffing on spectrum of ad9753
rev. b ad9753 e21e evaluation board the ad9753-eb is an evaluation board for the ad9753 tx dac. careful attention to layout and circuit design, combined with prototyping area, allows the user to easily and effectively evalu- ate the ad9753 in different modes of operation. referring to figures 34 and 35, the ad9753?s performance can be evaluated differentially or single-ended either using a trans- former, or directly coupling the output. to evaluate the output differentially using the transformer, it is recommended that either the mini-circuits t1-1t (through-hole) or the coilcraft ttwb-1-b (smt) be placed in the position of t1 on the evalua- tion board. to evaluate the output either single-ended or direct- coupled, remove the transformer and bridge either bl1 or bl2. the digital data to the ad9753 comes from two ribbon cables that interface to the 40-lead idc connectors p1 and p2. proper termi- nation or voltage scaling can be accomplished by installing the resistor pack networks rn1ern12. rn1, 4, 7, and 10 are 22 dip resistor packs and should be installed as they help reduce the digital edge rates and therefore peak current on the inputs. a single-ended clock can be applied via j3. by setting the se/ diff labeled jumpers j2, 3, 4, and 6, the input clock can be directed to the clk+/clke inputs of the ad9753 in either a single-ended or differential manner. if a differentially applied clock is desired, a mini-circuits t1-1t transformer should be used in the position of t2. note that with a single-ended square wave clock input, t2 must be removed. a clock can also be applied via the ribbon cable on port 1 (p1), pin 33. by inserting the edge jumper (jp1), this clock will be applied to the clk+ input of the ad9753. jp3 should be set in its se position in this application to bias clke to 1/2 the supply voltage. the ad9753?s pll clock multiplier can be enabled by inserting jp7 in the in position. as described in the typical performance characteristics and functional description sections, with the pll enabled, a clock at 1/2 the output data rate should be applied as described in the last paragraph. the pll takes care of the internal 2 frequency multiplication and all internal timing requirements. in this application, the plllock output indicates when lock is achieved on the pll. with the pll enabled, the div0 and div1 jumpers (jp8 and jp9) provide the pll divider ratio as described in table i. the pll is disabled when jp7 is in the ex setting. in this m ode, a clock at the speed of the output data rate must be applied to the clock inputs. internally, the clock is divided by 2. for data synchronization, a 1 clock is provided on the plllock pin in this application. care should be taken to read the timing requirements described earlier in the data sheet for optimum performance. with the pll disabled, the div0 and div1 jum pers define the mode (interleaved, noninterleaved) as described in table ii.
rev. b e22e ad9753 116 2b13 2 4 6 8 12 10 16 14 p2 p2 p2 p2 p2 p2 p2 p2 p2b13 1 215 2b12 p2b12 2 314 2b11 p2b11 3 413 2b10 p2b10 4 512 2b09 p2b09 5 611 2b08 p2b08 6 710 2b07 p2b07 7 89 2b06 p2b06 8 9 10 rn8 value rn7 value p2 p2 p2 p2 p2 p2 p2 p2 1 3 5 7 9 11 13 15 1 2 3 4 5 6 7 8 9 10 2b13 2b12 2b11 2b10 2b09 2b08 2b07 2b06 rn9 value 116 1b13 2 4 6 8 12 10 16 14 p1 p1 p1 p1 p1 p1 p1 p1 p1b13 1 215 1b12 p1b12 2 314 1b11 p1b11 3 413 1b10 p1b10 4 512 1b09 p1b09 5 611 1b08 p1b08 6 710 1b07 p1b07 7 89 1b06 p1b06 8 9 10 rn2 value rn1 value p1 p1 p1 p1 p1 p1 p1 p1 11 13 15 1 3 5 7 9 116 1b05 18 20 22 24 28 26 32 30 p1 p1 p1 p1 p1 p1 p1 p1 17 19 21 23 25 27 29 31 p1 p1 p1 p1 p1 p1 p1 p1 p1b05 1 215 1b04 p1b04 2 314 1b03 p1b03 3 413 1b02 p1b02 4 512 1b01 p1b01 5 611 1b00 p1b00 6 710 1o17 out15 7 89 out16 8 9 10 rn5 value rn4 value 36 34 40 38 p1 p1 p1 p1 p1 p1 p1 p1 33 35 37 39 25 26 27 28 29 30 31 32 33 34 35 36 u1 ad9751/ad9753/ad9755 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 22 23 24 21 12 11 10 9 8 3 2 1 7654 p2b12 msb p2b13 p2b11 p2b10 p2b09 p2b08 p2b07 p2b06 p2b05 p2b04 p2b03 p2b02 p2b01 p2b00 lsb s p 1 2 3 jp9 avdd plane 1 2 3 jp8 avdd_plane div0 div1 ab ab refio fsadj c12 0.1 f wht tp2 wht tp1 r1 1.91k dvdd plane p1b12 p1b11 p1b10 p1b09 p1b08 p1b07 p1b06 p1b05 p1b04 p1b03 p1b02 p1b01 p1b00 lsb p1b13 msb clkvdd ia ib p lpf c11 1.0 f r5 392 r10 opt 4 6 1 2 3 t1 bl1 bl2 1 2 i out j5 1 2 dgnd: 3,4,5 j1 dvdd plane clk+ clke reset 1 2 3 jp5 reset a b r4 50 wht tp3 out16 edge ext r3 50 c10 10pf r2 50 c9 10pf note: shield around r5 and c11 are connected to pllvdd plane pllvdd plane 1 2 3 4 5 6 7 8 9 10 1b13 1b12 1b11 1b10 1b09 1b08 1b07 1b06 rn3 value 1b05 1b04 1b03 1b02 1b01 1b00 1o16 rn6 value 1 2 3 4 5 6 7 8 9 10 1o17 1o15 jp10 blk tp4 blk tp5 blk tp6 116 2b05 18 20 22 24 28 26 32 30 p2 p2 p2 p2 p2 p2 p2 p2 17 19 21 23 25 27 29 31 p2 p2 p2 p2 p2 p2 p2 p2 p2b05 1 215 2b04 p2b04 2 314 2b03 p2b03 3 413 2b02 p2b02 4 512 2b01 p2b01 5 611 2b00 p2b00 6 710 7 89 8 9 10 rn11 value rn10 value 36 34 40 38 p2 p2 p2 p2 p2 p2 p2 p2 33 35 37 39 p2out15 p2out16 2b05 2b04 2b03 2b02 2b01 2b00 rn12 value 1 2 3 4 5 6 7 8 9 10 2out15 2out16 notes 1. all digital inputs from rn1ern12 must be of equal length. 2. all decoupling caps to be located as close as possible to dut, preferably under dut on bottom signal layer. 3. connect gnds under dut using bottom signal layer. 4. create plane capacitor with 0.007" dielectric between layers 2 and 3. blk tp7 blk tp8 blk tp9 p blk tp10 blk tp12 1o15 1o16 figure 34. evaluation board circuitry
rev. b ad9753 e23e s p 4 6 1 2 3 t2 1 2 1 2 3 jp6 clk+ a b c16 0.1 f p r9 1k jp4 df j3 clk p 1 2 3 jp2 a b se df jp1 edge out15 cklvdd r7 1k p 1 2 3 jp3 a b se df pgnd: 3, 4, 5 p r8 50 clke c13 10 f 10v tp13 dvdd plane blk p dvdd j8 l1 fbead 1 12 tp14 red dgnd j9 1 c14 10 f 10v tp15 avdd plane blk avdd j10 l2 fbead 1 12 tp16 red agnd j11 1 c15 10 f 10v tp17 clkvdd blk clkvdd j12 l3 fbead 1 12 tp11 red clkgnd j13 1 1 2 3 jp7 a b pllvdd plane c1 0.1 f dvdd plane pins 5, 6 c2 1 f c3 0.1 f c4 1 f pins 21, 22 c5 0.1 f pins 41, 44 c6 1 f avdd plane c7 0.1 f pins 45, 47 c8 1 f clkvdd p u1 bypass caps figure 35. evaluation board clock circuitry
rev. b e24e ad9753 figure 36. evaluation board, assembly?top figure 37. evaluation board, assembly?bottom
rev. b ad9753 e25e figure 38. evaluation board, top layer figure 39. evaluation board, layer 2, ground plane
rev. b e26e ad9753 figure 40. evaluation board, layer 3, power plane figure 41. evaluation board, bottom layer
rev. b ad9753 ?7 outline dimensions 48-lead low profile quad flat package [lqfp] (st-48) dimensions shown in millimeters top view (pins down) 1 12 13 25 24 36 37 48 0.27 0.22 0.17 0.50 bsc 7.00 bsc sq seating plane 1.60 max 0.75 0.60 0.45 view a 9.00 bsc sq pin 1 0.20 0.09 1.45 1.40 1.35 0.08 max coplanarity view a rotated 90 ccw seating plane 10 6 2 7 3.5 0 0.15 0.05 compliant to jedec standards ms-026bbc
rev. b ?8 c02251??/03(b) ad9753 revision history location page 9/03?ata sheet changed from rev. a to rev. b. changes to general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 changes to product highlights . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 changes to digital specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 changes to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 changes to figure 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 changes to figure 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 changes to functional description section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 changes to figure 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 changes to figure 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 changes to figure digital inputs section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 changes to figure 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1/03?ata sheet changed from rev. 0 to rev. a. changes to digital specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 changes to figure 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 changes to figure 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 changes to figure 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

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